Week 2 - Blink Using OS
cpu_cfg.h
1 /*
2 *********************************************************************************************************
3 * uC/CPU
4 * CPU CONFIGURATION & PORT LAYER
5 *
6 * (c) Copyright 2004-2013; Micrium, Inc.; Weston, FL
7 *
8 * All rights reserved. Protected by international copyright laws.
9 *
10 * uC/CPU is provided in source form to registered licensees ONLY. It is
11 * illegal to distribute this source code to any third party unless you receive
12 * written permission by an authorized Micrium representative. Knowledge of
13 * the source code may NOT be used to develop a similar product.
14 *
15 * Please help us continue to provide the Embedded community with the finest
16 * software available. Your honesty is greatly appreciated.
17 *
18 * You can find our product's user manual, API reference, release notes and
19 * more information at https://doc.micrium.com.
20 * You can contact us at www.micrium.com.
21 *********************************************************************************************************
22 */
23 
24 /*
25 *********************************************************************************************************
26 *
27 * CPU CONFIGURATION FILE
28 *
29 * TEMPLATE
30 *
31 * Filename : cpu_cfg.h
32 * Version : V1.30.00
33 * Programmer(s) : SR
34 * ITJ
35 * JBL
36 *********************************************************************************************************
37 */
38 
39 
40 /*
41 *********************************************************************************************************
42 * MODULE
43 *********************************************************************************************************
44 */
45 
46 #ifndef CPU_CFG_MODULE_PRESENT
47 #define CPU_CFG_MODULE_PRESENT
48 
49 
50 /*
51 *********************************************************************************************************
52 * CPU NAME CONFIGURATION
53 *
54 * Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
55 *
56 * (a) CPU host name storage
57 * (b) CPU host name API functions
58 *
59 * (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name,
60 * including the terminating NULL character.
61 *
62 * See also 'cpu_core.h GLOBAL VARIABLES Note #1'.
63 *********************************************************************************************************
64 */
65 
66  /* Configure CPU host name feature (see Note #1) : */
67 #define CPU_CFG_NAME_EN DEF_DISABLED
68  /* DEF_DISABLED CPU host name DISABLED */
69  /* DEF_ENABLED CPU host name ENABLED */
70 
71  /* Configure CPU host name ASCII string size ... */
72 #define CPU_CFG_NAME_SIZE 16 /* ... (see Note #2). */
73 
74 
75 /*
76 *********************************************************************************************************
77 * CPU TIMESTAMP CONFIGURATION
78 *
79 * Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
80 *
81 * (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
82 * (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
83 *
84 * (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
85 *
86 * CPU_WORD_SIZE_08 8-bit word size
87 * CPU_WORD_SIZE_16 16-bit word size
88 * CPU_WORD_SIZE_32 32-bit word size
89 * CPU_WORD_SIZE_64 64-bit word size
90 *
91 * (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
92 * (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
93 * size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
94 * size for CPU timestamp timers is 8-bits.
95 *
96 * See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
97 *********************************************************************************************************
98 */
99 
100  /* Configure CPU timestamp features (see Note #1) : */
101 #define CPU_CFG_TS_32_EN DEF_DISABLED
102 #define CPU_CFG_TS_64_EN DEF_DISABLED
103  /* DEF_DISABLED CPU timestamps DISABLED */
104  /* DEF_ENABLED CPU timestamps ENABLED */
105 
106  /* Configure CPU timestamp timer word size ... */
107  /* ... (see Note #2) : */
108 #define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_32
109 
110 
111 /*
112 *********************************************************************************************************
113 * CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
114 *
115 * Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts
116 * disabled time :
117 *
118 * (a) Enabled, if CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'
119 *
120 * (b) Disabled, if CPU_CFG_INT_DIS_MEAS_EN NOT #define'd in 'cpu_cfg.h'
121 *
122 * See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
123 *
124 * (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure &
125 * average the interrupts disabled time measurements overhead.
126 *
127 * See also 'cpu_core.c CPU_IntDisMeasInit() Note #3a'.
128 *********************************************************************************************************
129 */
130 
131 #if 0 /* Configure CPU interrupts disabled time ... */
132 #define CPU_CFG_INT_DIS_MEAS_EN /* ... measurements feature (see Note #1a). */
133 #endif
134 
135  /* Configure number of interrupts disabled overhead ... */
136 #define CPU_CFG_INT_DIS_MEAS_OVRHD_NBR 1u /* ... time measurements (see Note #1b). */
137 
138 
139 /*
140 *********************************************************************************************************
141 * CPU COUNT ZEROS CONFIGURATION
142 *
143 * Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
144 * function(s) in :
145 *
146 * (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
147 * 'cpu_cfg.h' to enable assembly-optimized function(s)
148 *
149 * (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
150 * 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
151 *
152 * (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
153 * function(s) in :
154 *
155 * (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
156 * 'cpu_cfg.h' to enable assembly-optimized function(s)
157 *
158 * (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
159 * 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
160 *********************************************************************************************************
161 */
162 
163 #if 1 /* Configure CPU count leading zeros bits ... */
164 #define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
165 #endif
166 
167 #if 0 /* Configure CPU count trailing zeros bits ... */
168 #define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
169 #endif
170 
171 
172 /*
173 *********************************************************************************************************
174 * CPU ENDIAN TYPE OVERRIDE
175 *
176 * Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
177 *
178 * (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
179 * octet @ lowest memory address)
180 * (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
181 * octet @ lowest memory address)
182 *
183 * (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
184 * See 'cpu.h CPU WORD CONFIGURATION Note #3' for details
185 *********************************************************************************************************
186 */
187 
188 #if 0
189 #define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_BIG /* Defines CPU data word-memory order (see Note #2). */
190 #endif
191 
192 
193 /*
194 *********************************************************************************************************
195 * CACHE MANAGEMENT
196 *
197 * Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
198 
199 *
200 * (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
201 * Cache are assumed to be configured and enabled by the time CPU_init() is called.
202 *********************************************************************************************************
203 */
204 
205 #define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED /* Defines CPU data word-memory order (see Note #1). */
206 
207 
208 /*
209 *********************************************************************************************************
210 * MODULE END
211 *********************************************************************************************************
212 */
213 
214 #endif /* End of CPU cfg module include. */
215 
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